SRAM Stability Characterization Using Tunable Ring Oscillators in 45nm CMOS

📋 论文概要

本文提出一种使用可调环形振荡器在45nm CMOS工艺中表征SRAM稳定性的方法。通过降低阵列供电电压VCELL来放大读取干扰效应，从而观察单元读取电流的变化，并评估单元失效前的行为。

💡 主要创新点

• 利用可调环形振荡器作为测试结构，实现对SRAM单元读取电流和稳定性的片上表征。
• 通过扫描VCELL电压，观察读取电流在不同电压下的变化，从而预测单元在低电压下的失效点。

🏷 关键词

📄 原文摘要

J. Watson, Yorktown Heights, NY 2 It is desirable to observe the cell read current at lower cell supplies. Lowering the array supply voltage VCELL can magnify the effect of read disturbance that raises the internal node voltage that stores a “0.” Doing so effectively weakens the corresponding pull-down transistor, allowing the internal node to rise up to a higher voltage. Figure 19.7.4a illustrates the variation in read current as VCELL is swept. A higher read current at nominal voltages does not necessarily translate to a higher read current at lower VCELL. Right before the cell fails data retention, denoted by the sharp drop in IREAD (at VCELL,CRIT), the corresponding pull-down transistor is at its weakest. Therefore, if a half cell can still exhibit high read current at that point, it must have a relatively strong pull-down and therefore good dynamic recoverability. It would be desirable to operate

👥 作者与机构

Jason Tsai1, Seng Oon Toh1, Zheng Guo1, Liang-Teck Pang1,2,

Tsu-Jae King Liu1, Borivoje Nikolic1 1 University of California, Berkeley, CA IBM T