A 5Gb/s Transceiver with an ADC-Based Feedforward CDR and CMA Adaptive Equalizer in 65nm CMOS

📋 论文概要

本文提出了一款基于ADC的5Gb/s收发器，采用前馈时钟数据恢复(CDR)和恒模算法(CMA)自适应均衡器，在65nm CMOS工艺中实现，旨在满足消费市场对高带宽和鲁棒性能的需求。

💡 主要创新点

• 首次在65nm CMOS中实现基于ADC的前馈CDR架构，无需传统模拟PLL即可完成时钟恢复。
• 采用CMA自适应均衡器，有效补偿信道损耗并适应变化信道条件，提升信号完整性。

🏷 关键词

📄 原文摘要

Yasumoto Tomita1, Takayuki Hamada1, Masaya Kibune1, Shuhei Ohmoto2, Keita Tateishi2, Oleksiy Tyshchenko3, Ali Sheikholeslami3, Tomokazu Higuchi2, Junji Ogawa1, Tamio Saito1, Hideki Ishida4, Kohtaroh Gotoh4 1 Fujitsu Laboratories, Kawasaki, Japan Fujitsu LSI Solutions, Kawasaki, Japan 3 University of Toronto, Toronto, Canada 4 Fujitsu Microelectronics, Akiruno, Japan 2 A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed

👥 作者与机构

Hisakatsu Yamaguchi1, Hirotaka Tamura1, Yoshiyasu Doi1,