A 320mV-to-1.2V On-Die Fine-Grained Reconfigurable Fabric for DSP/Media Accelerators in 32nm CMOS

📋 论文概要

该论文提出了一种在32nm CMOS工艺下工作电压从320mV到1.2V的片上细粒度可重构结构，用于DSP/媒体加速器。通过混合可配置逻辑块（CLB）阵列，实现了高能效的硬件加速，解决了可编程性与能效之间的平衡问题。

💡 主要创新点

• 实现了从320mV到1.2V的宽电压范围工作，支持超低电压下的高效运算。
• 采用细粒度可重构结构，结合混合CLB阵列，兼顾灵活性和面积效率。
• 针对DSP/媒体处理应用，在片上集成可重构加速器以降低功耗和成本。

🏷 关键词

📄 原文摘要

Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar Intel, Hillsboro, OR Computationally intensive DSP/media processing applications require specialized hardware accelerators to enable higher energy-efficiency on microprocessor platforms. On-die reconfigurable arrays enable flexible accelerators with dynamic on-the-fly programmability while amortizing die area and time-to-market costs across a wide range of workloads. An ultra-low-voltage fine-grained reconfigurable fabric consisting of a hybrid configurable logic block (CLB) array with process/voltage/temperature (PVT) variation-tolerant register file (Fig. 18.2.1), targeted for on-die acceleration of DSP/media algorithms on powerconstrained mobile microprocessors, is fabricated in 32nm high-k/metal-gate CMOS [1]. The CLB combines self-decoded look-up tables (LUTs) for random logic with reconfigurable arithmetic building blocks, hybrid 3:2 compressors

👥 作者与机构

Amit Agarwal, Sanu K Mathew, Steven K Hsu, Mark A Anders,