A 6.8mW 7.4Gb/s Clock-Forwarded Receiver with up to 300MHz Jitter Tracking in 65nm CMOS

📋 论文概要

本文提出了一种采用65nm CMOS工艺的时钟前向接收器，实现了6.8mW功耗和7.4Gb/s的数据速率。该接收器具有高达300MHz的抖动跟踪能力，解决了多链路接口中时钟抖动与数据相关的问题。

💡 主要创新点

• 提出了一种低功耗的时钟前向接收器架构，在65nm CMOS工艺下实现了6.8mW功耗和7.4Gb/s速率。
• 实现了高达300MHz的抖动跟踪带宽，有效抑制了时钟与数据之间的相关性抖动。
• 采用子速率时钟传输以减少损耗信道中的抖动放大，并通过频率倍乘和校准实现数据对齐。

🏷 关键词

📄 原文摘要

High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 - 20 data transceivers. Sub-rate clocks ameliorate jitter amplification in lossy channels. The forwarded clock must be frequency-multiplied and aligned with the data at each receiver. Per pin deskewing is done at startup [1]; the optimum deskew setting is stored and the calibration circuitry turned off during normal operation. Jitter on the forwarded clock is correlated with jitter on the data because both are generated by the same transmitter. Hence, jitter tolerance is improved by retiming the data with a clock that tracks correlated jitter on the forwarded clock [2]. However, since the delay of the data and clock paths typically differ by several UI, very high frequency jitter will appear out-of-phase at the receiver and should not be tracked. For a delay mismatch of L UI between

👥 作者与机构

Masum Hossain, Anthony Chan Carusone

University of Toronto, Toronto, Canada