A 30fJ/Conversion-Step 8b 0-to-10MS/s Asynchronous SAR ADC in 90nm CMOS

📋 论文概要

本文实现了一种8位异步逐次逼近寄存器（SAR）模数转换器（ADC），采用90nm CMOS工艺，在10kS/s至10MS/s的采样率范围内达到30fJ/转换步的卓越能效。该设计基于电荷再分配DAC结构，解决了宽采样率范围内保持高能效的问题。

💡 主要创新点

• 采用异步SAR架构，无需外部高速时钟，降低功耗并简化设计。
• 通过优化的开关电容网络和低功耗比较器，在0-10MS/s宽采样率范围内实现30fJ/转换步的极低能耗。

🏷 关键词

📄 原文摘要

power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power applications [1], [2]. This work describes the implementation of an 8bit asynchronous SAR ADC that achieves a 30fJ/Conversion-step power-efficiency for sampling rates between 10kS/s and 10MS/s. Figure 21.6.1 shows the implementation of the analog core of the 8bit ADC, based on a charge-redistribution DAC [1], [3]. The differential switched-capacitor network has three functions: sampling the analog input, applying an internal common-mode shift and implementing the DAC. On the negative edge of the sampling clock, the analog input value is stored on the capacitor array. The total

👥 作者与机构

Pieter Harpe, Cui Zhou, Xiaoyan Wang, Guido Dolmans, Harmke de Groot

Holst Centre-IMEC, Eindhoven, Netherlands Applications like wireless sensor nodes require ultra low-power receivers with