A Fractional-Sampling-Rate ADC-Based CDR with Feedforward Architecture in 65nm CMOS

📋 论文概要

该论文提出了一种基于分数采样率ADC的时钟数据恢复(CDR)架构，采用前馈结构替代传统的反馈相位跟踪环路，从而消除了压控振荡器或相位插值器等模拟电路，实现了全数字化的CDR设计。该方案在65nm CMOS工艺中实现，解决了模拟电路带来的设计复杂度和功耗问题。

💡 主要创新点

• 提出分数采样率ADC架构，以低于波特率的采样率进行数字化，降低ADC功耗和复杂度。
• 采用前馈结构替代传统反馈相位跟踪环路，实现全数字CDR，避免模拟相位调整电路。
• 在65nm CMOS工艺中验证了该架构的有效性，实现了高速数据恢复。

🏷 关键词

📄 原文摘要

CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sample the signal at 1× or 2× the baud rate. The 1× CDR aligns the sampling clock with the signal using a phase-tracking feedback loop [1-2], which requires a voltage-controlled oscillator or phase interpolator, both analog circuits, to adjust the phase of the sampling clock. To eliminate these analog circuits (and their phase control) in favor of an all-digital implementation, a blind-sampling ADC-based CDR (top of Fig. 8.6.1) samples the received signal at 2× without phase locking to the signal. The CDR then interpolates between the blind samples to obtain a new set

👥 作者与机构

Oleksiy Tyshchenko1, Ali Sheikholeslami1, Hirotaka Tamura2,

Yasumoto Tomita2, Hisakatsu Yamaguchi2, Masaya Kibune2, Takuji Yamamoto2 1 University of Toronto, Toronto, Canada Fujitsu Laboratories, Kawasaki, Japan 2 ADC-based