⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款采用90nm CMOS工艺的60GHz功率放大器，通过优化输入输出匹配网络和采用短截线拓扑结构，实现了高增益和20dBm的输出功率。该设计解决了毫米波频段功率放大器在CMOS工艺中增益和效率低下的问题。
input matching network of the second stage is matched with 50Ω to minimize loss while the output matching network is designed to deliver maximum output power using power contours which were determined by load-pull simulations. Note that each matching network uses a short-stub topology instead of a series line for loss minimization purposes [4]. This 2-stage common-source power amplifier was optimized to have gain of 10.5dB and P1dB at 13.7dBm, and the PAE of the 2-stage PA peaks at 10% when Pin is 6dBm at 60GHz. In wireless communications, high demand for superb video and audio quality increases the required transfer data rate. The unlicensed 7GHz bandwidth at Vband in North America has been drawing a lot of attention by companies and research institutions. Research topics done using CMOS fabrication, which appears to be a more appealing process due to its high level of integration, have been demonstrated to be a viable semiconductor for gigabit wireless at 60GHz
Chi Y Law, Anh-Vu Pham
University of California, Davis, CA