Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13µm CMOS

📋 论文概要

本文针对STT-MRAM存在的破坏性读取和高功耗写入问题，提出了负电阻读取方案（NRRS）和负电阻写入方案（NRWS）。NRRS通过设计保证非破坏性读取，NRWS则平均降低写入功耗。

💡 主要创新点

• 提出负电阻读取方案（NRRS），通过电路设计从根本上避免器件变化导致的破坏性读取。
• 提出负电阻写入方案（NRWS），能够平均降低写入功耗。

🏷 关键词

📄 原文摘要

random-access memory (MRAM) [1-3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access. However, two circuit-level challenges remain for STT-MRAM: potentially destructive read access due to device variation and a high-power write access. This paper presents two STT-MRAM access schemes: a negative-resistance read scheme (NRRS) that guarantees non-destructive read by design, and a negative-resistance write scheme (NRWS) that, on average, reduces the write power consumption by 10.5%. A fabricated and measured test-chip in 0.13µm CMOS confirms both properties. A simplified block-diagram of the STT-MRAM is shown in Fig. 14.1.1. The memory consists of storage cells and reference cells. A negative-resistan

👥 作者与机构

David Halupka1, Safeen Huda1, William Song1, Ali Sheikholeslami1,

Koji Tsunoda2, Chikako Yoshida2, Masaki Aoki2 1 University of Toronto, Toronto, Canada, Fujitsu Laboratories, Atsugi, Japan 2 Spin-torque-transfer (STT) magnetoresistive