A 2.1Mpixel 120frame/s CMOS Image Sensor with Column-Parallel ΔΣ ADC Architecture

📋 论文概要

该论文提出了一种采用列并行ΔΣ ADC架构的2.1百万像素、120帧/秒CMOS图像传感器，旨在满足高密度和高速度成像需求。通过将ΔΣ ADC应用于列并行结构，实现了高速度与低功耗的平衡。

💡 主要创新点

• 首次将ΔΣ ADC架构用于列并行CMOS图像传感器，实现2.1Mpixel分辨率下120fps的高速成像。
• 通过ΔΣ ADC的过采样和噪声整形特性，在列并行结构中保持了低功耗和高精度，克服了传统SAR、循环或单斜率ADC的局限。

🏷 关键词

📄 原文摘要

the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1-4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2-6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic

👥 作者与机构

Youngcheol Chae1, Jimin Cheon1, Seunghyun Lim1, Dongmyung Lee1,

Minho Kwon2, Kwisung Yoo2, Wunki Jung2, Dong-Hun Lee2, Seogheon Ham2, Gunhee Han1 1 Yonsei University, Seoul, Korea, Samsung Electronics, Yongin, Korea 2 Over the last few years,