A 32mW 7.4Gb/s Protocol-Agile Source-SeriesTerminated Transmitter in 45nm CMOS SOI

📋 论文概要

本文提出一种采用源串联端接（SST）结构的协议敏捷发射器，在45nm CMOS SOI工艺上实现了7.4Gb/s的数据率和32mW的低功耗。解决了传统CML驱动器功耗高的问题，同时克服了SST在灵活摆幅、恒流均衡和DC耦合电压标准支持方面的困难。

💡 主要创新点

• 采用源串联端接结构替代传统CML驱动器，将输出级功耗降低至CML的1/4。
• 实现了协议敏捷性，能够灵活调节输出摆幅和进行恒流均衡，支持多种协议标准。
• 在保持低功耗的同时支持DC耦合电压标准，提升了多协议SerDes的兼容性。

🏷 关键词

📄 原文摘要

Teva Stone1, Barry Daly1 1 Rambus, Chapel Hill, NC, Rambus, Bangalore, India 2 Source-series-terminated (SST) transmitters consume ¼ the output stage power of CML drivers [1], but their adoption in industry-standard multi-protocol SerDes has been stunted by difficulties in achieving flexible swings, constant current equalization, and supporting DC-coupled voltage standards drafted with CML in mind. Fundamentally, CML drivers separate the termination control from the switching devices, allowing current summing techniques to implement output level control and transmitter equalization (EQ). In this paper, the architecture and circuits of an equally flexible SST transmitter is presented that overcomes these challenges through the use of ground regulation, P-to-N shunting legs, and partially weighted segments. The clocks and datapath dissipate 32mW at 7.4Gb/s with an 800mV differential swing. Target protocols include PCIe Gen1/2,

👥 作者与机构

Wayne D Dettloff1, John C Eble1, Lei Luo1, Pravin Kumar2, Fred Heaton1,