A 2Gb/s 1.8pJ/b/chip Inductive-Coupling ThroughChip Bus for 128-Die NAND-Flash Memory Stacking

📋 论文概要

该论文提出了一种用于128层NAND闪存堆叠的感应耦合穿芯片总线，通过螺旋楼梯堆叠方案替代传统阶梯式堆叠，无需间隔芯片，将总高度从6.0mm降至3.9mm，平均通信距离缩短，传输功耗降低至60%。

💡 主要创新点

• 提出螺旋楼梯堆叠方案，无需间隔芯片，显著降低堆叠高度。
• 采用感应耦合收发器实现中继传输，平均通信距离缩短，传输功耗降低至60%。

🏷 关键词

📄 原文摘要

NAND Flash memory chips and 1 controller chip are stacked in a single package for SSD applications (Fig. 24.5.1). The controller chip accesses a random memory chip by relayed transmission using inductive-coupling transceivers [1,2]. A conventional terraced chip stacking scheme [1] requires spacer chips to provide bonding space. The total height would be 6.0mm. A spiral stair stacking scheme is proposed that requires no spacer chips. The total height is reduced to 3.9mm. Average communication distance is shortened, and transmission power is reduced to 60%. A coil of 1.1mm diameter, larger than conventional, is employed to extend the communication distance for enabling transmission relayed at every 8th chip. Number of transceivers activated for chip access is reduced to 1/4 compared to [1,2] where transmission was relayed at every 2nd chip with a coil of 0.2mm diameter. Although the transmission power

👥 作者与机构

Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda

Keio University, Yokohama, Japan