Spur-Reduction Techniques for PLLs Using SubSampling Phase Detection

📋 论文概要

该论文提出基于子采样相位检测的参考杂散抑制技术，在2.2GHz锁相环中实现了-80dBc的参考杂散，并支持高达1/2的环路带宽与参考频率之比。解决了传统PLL在高带宽下参考杂散恶化的问题。

💡 主要创新点

• 提出子采样相位检测器，通过降低鉴相器上的纹波电压来抑制参考杂散。
• 实现了高环路带宽与参考频率比（fBW/fref=1/2）下的低杂散性能，突破了传统PLL的带宽限制。

🏷 关键词

📄 原文摘要

University of Twente, Enschede, Netherlands National Semiconductor, Santa Clara, CA 2 In PLL designs, a wide loop bandwidth is often desired as it offers fast settling time, reduces on-chip loop filter area and sensitivity of the VCO to pulling. The reference spur is a major issue when the bandwidth is increased, because ripples on the VCO control line undergo less filtering by the loop filter. This paper proposes design techniques based on sub-sampling phase detection to reduce the reference spur of a 2.2GHz PLL to -80dBc at a high loop-bandwidth-to-reference-frequency ratio (fBW/fref) of 1/20. In a charge-pump (CP) PLL, the mismatch between the CP up current source IUP and down current source IDN is often the major source of reference spur. In a conventional phase-frequency-detector (PFD)/CP as shown in Fig. 26.4.1(a), the PFD converts the VCO phase error into the IUP and IDN switch-on time difference

👥 作者与机构

Xiang Gao1, Eric A. M. Klumperink1, Gerard Socci2, Mounir Bohsali2, Bram Nauta1