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该论文提出了一种采用65nm CMOS工艺的2.4GHz功率放大器，通过分布式LC功率合成网络和改进的线性化技术，实现了31.5dBm的输出功率。解决了CMOS工艺在低电源电压、有损衬底和低击穿电压下实现高线性度和高输出功率的难题。
greatest challenges facing the designers of complex wireless SoCs. Recently, there has been a significant effort to implement PA’s in CMOS [1-4]. The 802.11g standard utilizes OFDM modulation, which has a very high peak-to-average ratio (PAR) and therefore requires a highly linear PA. In addition, WLAN SoCs are evolving to accommodate more advanced applications, like the transmission and reception of multiple streams of high-definition video across long distances. This requires a higher linear transmit power. However, the low power supply, lossy substrate and lower breakdown voltage make the design of a linear, high power, high efficiency and reliable CMOS PA quite challenging. In this paper, a linear 65nm CMOS PA operating at 3.3V supply with an on-chip distributed LC power combining network and improved linearization is presented. The result is the highest
Ali Afsahi1,2, Arya Behzad2, Lawrence E. Larson1, 1
University of California, San Diego, CA Broadcom, San Diego, CA 2 The integration of the power amplifier (PA) is one of the