A 40GS/s 6b ADC in 65nm CMOS

📋 论文概要

该论文提出了一款在65nm CMOS工艺下实现的40GS/s 6位ADC，旨在满足100G光传输系统中对高速、低抖动采样的需求，解决了此前ADC采样率不足和采样抖动较大的问题。

💡 主要创新点

• 采用时间交织架构，实现了40GS/s的超高采样率，同时保持6位分辨率。
• 通过优化时钟分配和降低采样抖动，提升了ADC在高速下的动态性能。

🏷 关键词

📄 原文摘要

Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang Nortel, Ottawa, Canada Progress in 40Gb/s optical dual- polarization (DP) QPSK systems inspired an idea of 100G transmission by optical frequency division multiplexing (FDM) of QPSK-modulated channels [1]. A practical solution suggests two 58Gb/s DP QPSK channels, spaced by 50GHz (Fig. 21.7.1). The challenge is in implementing a 6b ADC operating at sampling rate of 29Gs/s, as compared to 24Gs/s reported before [2]. The other challenge is reduction of ADC sampling jitter. In an interleaved architecture, jitter is limited by the timing mismatch between the clocks of T&H circuits. While initial timing error is compensated during ADC calibration, its spread over the input frequency range and drift may still impact jitter performance. This paper presents, to our knowledge for the first time, a 6b

👥 作者与机构

Yuriy M Greshishchev, Jeorge Aguirre, Marinette Besson,