A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for Wireless HD Applications

📋 论文概要

提出一个完全集成的频率合成器（PLL），采用65nm CMOS工艺，符合IEEE 802.15.3c标准，可同时输出20GHz正交信号和40GHz差分信号，调谐范围达17.9%，覆盖无线HD应用所需的全部频段。

💡 主要创新点

• 实现17.5-20.94GHz和35-41.88GHz双频段输出的PLL，满足多模无线HD需求。
• 采用65nm标准CMOS工艺，达到17.9%的宽调谐范围，覆盖IEEE 802.15.3c全频段并留有工业裕量。

🏷 关键词

📄 原文摘要

Cedric Dufis1, Pierre Busson1, Pierre Vincent2, Didier Belot1, Pascal Urard1 1 STMicroelectronics, Crolles, France CEA-LETI-Minatec, Grenoble, France 3 STMicroelectronics, Grenoble, France 2 This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. This frequency synthesizer is fully compliant with IEEE 802.15.3c normalization [1-4]. This PLL delivers a quadrature LO signal around 20GHz and a differential LO signal around 40GHz and has 17.9% tuning range. The wide tuning range of 17.9% permits to cover the full IEEE 802.15.3c band with industrial margin. The phase noise is -100dBc/Hz at 1MHz offset and the total power dissipation is only 80mW including the output buffers and amplifiers. Short-range wireless multi-Gb/sec communication systems use the mm-wave band of 57GHz to 66GHz, according to the IEEE 802.15.3c normalization. The frequency synthesis is one of the key elements for these transceivers. Indeed,

👥 作者与机构

Olivier Richard1, Alexandre Siligaris2, Franck Badets3, Cedric Dehos2,