A 78mW 11.8Gb/s Serial Link Transceiver with Adaptive RX Equalization and Baud-Rate CDR in 32nm CMOS

📋 论文概要

本文提出一款采用32nm CMOS工艺的11.8Gb/s串行链路收发器，功耗仅78mW。通过自适应接收均衡和波特率时钟数据恢复技术，解决了高速串行IO在功耗和面积上的挑战。

💡 主要创新点

• 采用自适应接收均衡技术，能够动态补偿信道损耗，提升信号完整性。
• 实现波特率时钟数据恢复，无需额外参考时钟，降低功耗和面积。
• 整体收发器在78mW功耗下达成11.8Gb/s数据率，体现了先进的低功耗设计。

🏷 关键词

📄 原文摘要

Doug Gambetta1, Sujatha Gowder1, Sitaraman Iyer1, Rohit Kumar1, Peter Kwok1, Renuka Krishnamurthy1, Chien-chun Lin1, Ravindran Mohanavelu1, Roan Nicholson1, Jeff Ou1, Marcus Pasquarella1, Kavitha Prasad1, Hendra Rustam1, Luke Tong1, Amanda Tran1, John Wu1, Xuguang Zhang1 1 Intel, Santa Clara, CA Intel, Hillsboro, OR 2 The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all, by the need to achieve stringent bit error rates in the presence of interconnect constraints such as channel loss, impedance discontinuities induced by package and connectors, and crosstalk effects due to routing limitations in the package and on the motherboard. To effectively meet these challenges, the serial IO architecture has evolved to include more complex equalization schemes.

👥 作者与机构

Fulvio Spagna1, Lidong Chen1, Mamatha Deshpande1, Yongping Fan2,