A 2.6mW 6b 2.2GS/s 4-times Interleaved Fully Dynamic Pipelined ADC in 40nm Digital CMOS

📋 论文概要

该论文提出了一种四通道交织的6位2.2GS/s流水线ADC，采用全动态流水线架构和折叠前端，在40nm CMOS工艺中实现极低功耗2.6mW。通过动态流水线减少输入电容并实现高速量化，同时折叠前端将所需校准工作量减半。

💡 主要创新点

• 采用全动态流水线架构，实现超低功耗高速量化，且输入电容小。
• 提出折叠前端技术，对输入信号进行采样和整流，同时去除共模电压，有效降低校准复杂度。
• 四通道交织结构在保持高速的同时进一步降低校准需求。

🏷 关键词

📄 原文摘要

fast ADC with low resolution. We present a four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, for these requirements. Dynamic pipelined conversion enables low power quantization at high speed with low input capacitance but requires calibration. A folding front-end halves the required calibration effort. Figure 16.3.1 shows a simplified schematic of the folding front-end and its waveforms. It samples and rectifies the input signal while removing its common-mode. When the S1 switches are closed the input voltages are tracked across Cs. At a falling φ1 edge the charges on Cs are fixed. Their bottom plates are at ground and the top plates at their sampled input voltage, neglecting charge injection. Closing S2 shorts the top plates and generates the differential

👥 作者与机构

Bob Verbruggen1,2, Jan Craninckx1, Maarten Kuijk2,

Piet Wambacq1,2, Geert Van der Plas1 1 IMEC, Leuven, Belgium Vrije Universiteit Brussel, Elsene, Belgium 2 Communication in the unlicensed frequency band around 60GHz requires a very