A 4.1Tb/s Bisection-Bandwidth 560Gb/s/W Streaming Circuit-Switched 8×8 Mesh Network-on-Chip in 45nm CMOS

📋 论文概要

本文提出了一种基于电路交换的8×8 mesh网络芯片，在45nm CMOS工艺上实现了4.1Tb/s对分带宽和560Gb/s/W能效。通过消除路由过程中的数据存储，解决了传统分组交换网络能效低的问题。

💡 主要创新点

• 采用电路交换而非分组交换，避免了数据在路由过程中的存储，从而大幅提升能效。
• 实现了512b数据宽度与1b数据互连的仲裁逻辑，在保证高带宽的同时优化了功耗。
• 在8×8 mesh拓扑中集成了高效的流式电路交换机制，支持多核处理器间低延迟通信。

🏷 关键词

📄 原文摘要

core-to-core communication, are key to enabling future tera-scale multi-core processors. Packetswitched 2D mesh networks provide efficient interconnect utilization, low latencies and high throughputs, but suffer from low energy efficiency due to data storage during routing [1-2]. Circuit-switched data transfer achieves both high bandwidth and energy efficiency by eliminating intra-route data storage [3]. An 8×8 mesh circuit-switched network-on-chip, consisting of arbitration logic for 512b data width with 1b data interconnect, is fabricated in 45nm high-κ metalgate CMOS [4]. Scaling data width measurements to 512b, the circuits achieve 560Gb/s/W energy efficiency, 4.1Tb/s bisection bandwidth, and 11ns diagonal corner-to-corner fall-through latency. Reconfigurable router circuits allow

👥 作者与机构

Mark A Anders, Himanshu Kaul, Steven K Hsu, Amit Agarwal,

Sanu K Mathew, Farhana Sheikh, Ram K Krishnamurthy, Shekhar Borkar Intel, Hillsboro, OR Interconnect networks, for high-bandwidth energy-efficient