⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一种32nm全集成可重构开关电容DC-DC转换器，在0.55W/mm²的功率密度下实现81%的效率。通过利用标准单元的逻辑物理顺序，简化了驱动设计，并支持多种工作模式以优化性能。
and drain voltages can reside anywhere among Vi, (Vi/2+Vo/2), Vo, and (Vo/2) in the 3 modes of operation. Fortunately however, the physical/logical ordering of the standard cells can be leveraged to realize a simplified driver design. Specifically, since C1 is always intended to be stacked above C2, C1_pos and C1_neg can be used as virtual rails for a “flying” inverter INV5 (Fig. 10.8.2). By connecting the input of INV5 to C2_pos, M5 is automatically controlled by the actions of the other switches on the two flying capacitors. 2 With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DCDC converters is not only difficult due to supply impedance concerns, but al
Hanh-Phuc Le1, Michael Seeman1, Seth R. Sanders1, Visvesh Sathe2,
Samuel Naffziger2, Elad Alon1 1 University of California, Berkeley, CA AMD, Fort Collins, CO Driving switch M5 is even more challenging since its source