An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR Inductive-Coupling Interface Between 65nm CMOS GPU and 0.1µm DRAM

📋 论文概要

本文提出了一种基于电感耦合的QDR接口，在65nm CMOS GPU和0.1µm DRAM之间实现8Tb/s的总带宽，能效为1pJ/b，面积效率为0.8mm²/Tb/s。通过正交时钟和XOR操作进行四倍数据率复用/解复用，补偿GPU与DRAM之间的晶体管性能差距，并用注入锁定VCO从数据中恢复时钟。

💡 主要创新点

• 采用电感耦合实现1024位并行收发，每链路8Gb/s，总带宽8Tb/s。
• 提出QDR技术，在DRAM侧使用正交时钟和XOR操作进行四倍数据率复用/解复用，补偿工艺差距。
• 使用注入锁定VCO从接收数据中恢复时钟，无需额外时钟链路，降低功耗和面积。

🏷 关键词

📄 原文摘要

This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating at 8Gb/s/link. In the DRAM transceiver, data are multiplexed and demultiplexed by using a quadrature clock and XOR operation. This circuit technique for QDR compensates for transistor performance gap between the GPU and the DRAM to achieve 8Gb/s bandwidth. The clock for data retiming is recovered from the received data by using an injection-lock VCO. Clock links and clock distribution circuits are not needed, resulting in small layout area of 0.8mm2/Tb/s. Frontend of the transceiver is implemented using NMOS CML circuits with adaptive bias control. The transceiver’s sensitivity to PVT variations is small, enabling all the 1024 parallel transceivers to operate at BER<10-16. It also reduces the design

👥 作者与机构

Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda

Keio University, Yokohama, Japan