A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation

📋 论文概要

本文提出了一种10位100MS/s的逐次逼近寄存器（SAR）模数转换器（ADC），采用二进制缩放的误差补偿技术，通过三个补偿电容来容忍每个位周期至少12.5%的建立误差，从而在低功耗下实现高速高精度转换。

💡 主要创新点

• 提出二进制缩放的误差补偿方法，利用三个补偿电容有效容忍位周期内的建立误差，提高ADC的鲁棒性。
• 通过优化电容阵列和补偿电容的尺寸，在保持低功耗（1.13mW）的同时实现100MS/s的采样率。

🏷 关键词

📄 原文摘要

with three compensative capacitors can tolerate settling error of at least 12.5% in each bit cycle. Note the precise error tolerance range depends on where the wrong decision occurs. The amplitude of the input signal swing is Vref×(C1to9/Ctotal) where Vref is the reference voltage range, C1to9 is the total capacitance of C1 to C9, Ctotal is the total capacitance including C1to9, the three compensative capacitors and the parasitic capacitance at the comparator input terminal. 2 In recent years, due to the improvements in CMOS technologies, medium resolution (8 to 10b) SAR ADCs have been able to achieve sampling rates of several tens of MS/s with excellent power efficiency and small area [1]-[4]. When the sampling rate increases, the SAR ADCs suffer from settling issues. In a typical

👥 作者与机构

Chun-Cheng Liu1, Soon-Jyh Chang1, Guan-Ying Huang1, Ying-Zu Lin1,

Chung-Ming Huang2, Chih-Hao Huang2, Linkai Bu2, Chih-Chung Tsai2 1 National Cheng-Kung University, Tainan, Taiwan Himax Technologies, Tainan, Taiwan proposed case, the SAR ADC