A 32kB 2R/1W L1 Data Cache in 45nm SOI Technology for the POWER7TM Processor

📋 论文概要

本文为POWER7处理器设计了一个32kB的L1数据缓存，采用45nm SOI工艺，支持两周期内同时进行两个独立读和一个写操作。通过将缓存组织成四个8kB的bank，满足了乱序和多线程计算对高并行性多端口存储的需求。

💡 主要创新点

• 实现了2R/1W（两读一写）的多端口L1数据缓存架构，支持高并行访问。
• 采用45nm SOI工艺和bank组织方式，在保证速度的同时提高了存储密度。
• 通过两周期背靠背操作设计，优化了读写冲突处理，提升了流水线效率。

🏷 关键词

📄 原文摘要

Wolfgang Penth1, Thomas Froehnel1, Stefan Buettner1, Otto Torreiter1, Martin Eckert1, Jose Paredes2, David Hrusecky2, David Ray2, Miles Canada3 1 IBM, Boeblingen, Germany IBM, Austin, TX 3 IBM, Burlington, VT 2 Increasing demand for parallelism due to out-of-order and multi-threading computation requires fast and dense arrays with multi-port capabilities. The loadstore-unit (LSU) of the POWER7TM microprocessor core has a 32kB L1 data cache composed of four 8kB blocks. In a two-cycle back-to-back operation it supports concurrently two independent read and one write operations. Organized in banks of 16 cells each, the two reads operate independently in any of these banks, including two reads within the same bank, even the same cell. A bank selected for write is blocked for any read operation. If read and write collide within the same bank, collision-control circuitry provides write-over-read

👥 作者与机构

Juergen Pille1, Dieter Wendel1, Otto Wagner1, Rolf Sautter1,