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该论文提出了一种在45nm CMOS工艺下实现的电流舵音频DAC，实现了110dB SNR和0.5mW的低功耗。通过提高调制器分辨率来降低带外噪声，从而减少对模拟后滤波器和时钟抖动的敏感度，实现低成本低功耗设计。
longer battery life and lower cost. Achieving low out–of-band noise (OBN) is one of the key elements in designing inexpensive, low-power and robust audio DACs. Lowering OBN reduces the sensitivity to circuit mismatch, glitch energy and clock jitter. The need for an expensive analog post filter that requires high bias currents can be eliminated altogether. Requirements on the application clock are relaxed and low-cost PLLs can be used in the system. To reduce OBN, one needs to increase modulator resolution. The popular method is to increase the number of unit weighted elements in an oversampled DAC. This results in high digital complexity, inter-symbol-interference (ISI) and tonal problems when shaping mismatch errors. Reported multi-bit oversampling audio DACs [1, 2] use noiseshaped segmentation to split a main mo
Rahmi Hezar1, Lars Risbo2, Halil Kiper1, Mounir Fares1, Baher Haroun1,
Gangadhar Burra1, Gabriel Gomez1 1 Texas Instruments, Dallas, TX Texas Instruments, Copenhagen, Denmark 2 Mobile consumer audio applications are demanding higher performance,