⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一款基于34nm工艺的3bit/cell 32Gb NAND闪存，实现了6MB/s的编程吞吐量，并引入动态2b/cell块配置技术以平衡密度与可靠性，解决了高密度闪存中编程速度与数据保持能力的矛盾。
C. Lattaro1, C. Musilli1, D. Rivers2, E. Sirizotti1, F. Paolini1, G. Imondi1, G. Naso1, G. Santin1, L. Botticchio1, L. De Santis1, L. Pilolli1, M.L. Gallese1, M. Incarnati1, M. Tiburzi1, P. Conenna1, S. Perugini1, V. Moschiano1, W. Di Francesco1, M. Goldman3, C. Haid3, D. Di Cicco1, D. Orlandi1, F. Rori1, M. Rossini1, T. Vali1, R. Ghodsi4, F. Roohparvar4 1 Micron, Avezzano, Italy Micron, Boise, ID 3 Intel, Folsom, CA 4 Micron, San Jose, CA 2 In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floatin
G.G. Marotta1, A. Macerola1, A. D’Alessandro1, A. Torsi1, C. Cerafogli1,