A Low-Noise Frequency Synthesizer for Infrastructure Applications

📋 论文概要

本文设计了一款针对无线基础设施应用的低噪声频率合成器芯片，解决了本地振荡器相位噪声和切换速度的关键性能瓶颈，实现了高性能集成。

💡 主要创新点

• 采用低噪声VCO和PLL架构实现极低相位噪声，满足基础设施收发器的严格性能要求。
• 集成快速频率切换能力，以支持高速率通信场景。
• 通过片上集成技术降低系统成本和复杂度，替代传统分立方案。

🏷 关键词

📄 原文摘要

David Stegmeir, Li Jin RFMD, San Jose, CA Because of higher performance requirements, infrastructure transceivers have historically employed lower levels of on-chip integration than their handset counterparts. One of the main limiting components preventing on-chip integration is the Local Oscillator (LO). The phase noise performance of the LO and its switching speed are some of the most critical performance metrics for an infrastructure transceiver. The work presented here is a frequency synthesizer IC targeted at wireless infrastructure applications. Previous works on high-performance VCO design either did not address the large tuning bandwidth requirements

👥 作者与机构

Shayan Farahvash, William Roberts, Jake Easter, Rachel Wei,