A 86MHz-to-12GHz Digital-Intensive PhaseModulated Fractional-N PLL Using a 15pJ/Shot 5ps TDC in 40nm digital CMOS

📋 论文概要

本文提出了一种数字密集型、可重构的分数-N锁相环，覆盖86MHz至12GHz频率范围。通过两步背景校准实现了面积高效（0.01mm²）且能量高效（15pJ/Shot）的5ps分辨率TDC，并利用静态失配校准将DAC面积减小4倍。该PLL支持数字相位调制，环路带宽可调，在7GHz时实现了-144dBc/Hz@20MHz偏移的相位噪声。

💡 主要创新点

• 采用两步背景校准技术，实现了5ps分辨率、15pJ/Shot能量效率的TDC，面积仅0.01mm²。
• 通过静态失配校准将DAC面积降低4倍，同时保持性能。

📄 原文摘要

IMEC, Leuven, Belgium K.U. Leuven, Leuven, Belgium 2 Digital-intensive PLL architectures emerge [1]-[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz12GHz synthesizer. Simple 2-step background calibration enables the use of an area- and energy-efficient 5ps TDC (0.01mm2 and 15-pJ per-shot). Static mismatch calibration lowers the DAC area 4 times. The PLL, featuring digital phase modulation is fully reconfigurable, with loop bandwidth ranging from 0.1-2MHz. At 7GHz, the 0.28mm2 PLL achieves -144dBc/Hz phase noise at 20MHz offset, for 0.56ps jitter in 40MHz bandwidth, consuming less than 30mW. A PLL architecture with fractional divider (Fig. 26.7.1) is chosen over a dividerless one, to relax linearity requirements for the TDC [4]. For low in-band phasenoise, a fine resolution (5ps) and high dynamic range (14bit) TDC is needed, favoring a coarse-fine architecture. However, as recognized in [5], unlike voltage,

👥 作者与机构

Jonathan Borremans1, Kameswaran Vengattaramane1,2, Vito Giannini1, Jan Craninckx1