A 0.06mm2 8.9b ENOB 40MS/s Pipelined SAR ADC in 65nm CMOS

📋 论文概要

本文提出一种65nm CMOS工艺下的流水线逐次逼近（Pipelined SAR）ADC，面积为0.06mm²，在40MS/s采样率下实现8.9位有效位数。通过结合流水线和SAR结构，解决了传统SAR ADC中电容阵列面积过大的问题。

💡 主要创新点

• 采用流水线SAR架构，将高分辨率SAR分解为多级流水线，减少每级所需电容数量，从而显著缩小芯片面积。
• 通过优化电容阵列和电荷共享技术，在保持较小单位电容（10fF）的同时提高了有效位数，克服了小电容带来的匹配和噪声问题。

🏷 关键词

📄 原文摘要

In 10b SAR ADCs, one of the major design challenges is the large number of capacitors for implementing the capacitor array. A large unit capacitance should be used due to the design constraint of capacitor mismatches and/or layout design rules. As a result, the total capacitance is typically much larger than what is required by kT/C noise. In [1], a 10-bit SAR ADC is presented that achieves an area of 0.075mm2 with a charge redistribution architecture using a small unit capacitance of 10fF, while SNDR is low becasue of using such a small unit capacitance. The charge-sharing SAR proposed in [2] allows a relatively large unit capacitance by reducing the required number of capacitors. However, it requires a large (10pF) S/H capacitor for precise operation. The ADC presented in [3] needs large logic circuits to implement a complex calibration. The converter presented in [4] is a pipelined ADC. The pipelined architecture overcomes the unit

👥 作者与机构

Masanori Furuta, Mai Nozawa, Tetsuro Itakura

Toshiba, Kawasaki, Japan