A Configurable SRAM with Constant-Negative-Level Write Buffer for Low-Voltage Operation with 0.149µm2 Cell in 32nm High-κ Metal-Gate CMOS

📋 论文概要

本文提出了一种适用于低电压操作的可配置SRAM，通过恒定负电平写缓冲器（CNL-WB）和电平可编程字线驱动器（LPWD-SS）来改善写裕度。CNL-WB利用复制位线技术自动调整位线电平，支持4-512个单元/位线的配置范围；LPWD-SS在单电源下优化了干扰与写裕度的权衡。

💡 主要创新点

• 恒定负电平写缓冲器（CNL-WB）通过复制位线技术自动调整位线电平，适用于宽范围配置，显著提升写裕度。
• 电平可编程字线驱动器（LPWD-SS）在单电源下优化了读取干扰与写入裕度的折中，支持低电压操作。

📄 原文摘要

Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe Toshiba Semiconductor, Kawasaki, Japan This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-κ metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.

👥 作者与机构

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki,