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该论文提出了一款在65nm CMOS工艺下实现的12.5Gb/s完整收发器，包括CDR、MUX/DEMUX和全局时钟分配，总功耗仅12.3mW，能效达到0.98mW/(Gb/s)（低于1pJ/b），解决了高速接口中功耗效率的长期挑战。
power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate
Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki,
Takashi Takemoto, Fumio Yuki, Tatsuya Saito Hitachi, Tokyo, Japan For the people involved with multi-Gb/s chip-to-chip serial links, reducing