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ISSCC 2010Session 18 · POWER EFFICIENT MEDIA PROCESSINGPower Management

A 59.5mW Scalable/Multi-View Video Decoder Chip for Quad/3D Full HDTV and Video Streaming Applications

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📋 论文概要

本文提出了全球首款同时支持H.264/AVC High Profile、多视图视频编码(MVC)和可扩展视频编码(SVC)的视频解码器芯片,功耗仅59.5mW,可用于QFHD、3D/多视图电视及视频流应用。该芯片通过创新的块流水线调度和架构解决了多标准兼容与低功耗的挑战。

💡 主要创新点

核心指标
59.5mW功耗
重要性
发表年份
ISSCC 2010

🏷 关键词

视频解码器多视图视频编码可扩展视频编码低功耗H.264

📄 原文摘要

applications are emerging. The first involves more vivid perceptual experience and is leading to the next generation of TV specifications – Quad Full HD (QFHD, 4096×2160p) and 3D/multi-view TV. The second is the scalable broadcasting and streaming of video. To support these applications, the worldwide first video decoder that supports three most advanced video coding standards – H.264/AVC High Profile, multiview video coding (MVC), and scalable video coding (SVC), is realized. Three main design challenges are encountered. 1) Conventional block-pipelining scheduling and architecture cannot efficiently support diverse SVC decoding schemes. 2) Up to 300Mbps high data-rate entropy decoding is required for QFHD, which is 2.3× that achieved in current state-of-the-art design [1]. 3) An

👥 作者与机构

Tzu-Der Chuang, Pei-Kuei Tsung, Pin-Chih Lin, Lo-Mei Chang,

Tsung-Chuan Ma, Yi-Hau Chen, Liang-Gee Chen National Taiwan Univeristy, Taipei, Taiwan With advances in video coding technology, two main streams of multimedia

分类:Power Management · 年份:ISSCC 2010