⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种用于偏移补偿的位线传感放大器，旨在解决低电压DRAM中因位线与字线间耦合电容等噪声导致的传感失败问题。通过该放大器，可以在低VCORE条件下实现可靠的传感操作。
DRAM chips [1]. To satisfy this need, it is desirable to use a low VCORE in the DRAM core, even though with such a low voltage it is difficult to sense the cell signal due to an insufficient sensing margin in high density DRAM [2-3]. When the bitline (BL) sense amp (BLSA) starts the sensing operation, all the BLs in the cell array go to the data transition stage. This leads to sensing noise in the BLSA, resulting in a sensing failure. There are several noise sources that contribute to this sensing failure, but the major noise source is the coupling capacitance between the BL and the wordline (WL) [4], which leads to a cell MAT array noise as shown by the data patterns. We develop a BLSA to compensate for this MAT sensing noise. In this experiment, we fabricate a 68nm DRAM chip that shows
Myoung Jin Lee, Ki Myung Kyung, Hyung Sik Won, Myoung Su Lee, Kun Woo Park
Hynix Semiconductor, Icheon, Korea The industry has continuously demanded lower voltages and higher densities in