⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种针对80核处理器的片内变化感知动态电压频率缩放核心映射和线程跳跃技术，解决了多核处理器中由于工艺变化导致的性能和功耗不均问题。通过动态调整核心映射和线程分配，实现了更高的能效和性能一致性。
Tiju Jacob2, Keith Bowman1, Jason Howard1, James Tschanz1, Vasantha Erraguntla2, Nitin Borkar1, Vivek De1, Shekhar Borkar1 1 Intel, Hillsboro, OR Intel, Bangalore, India 2 Many-core processors with on-die network-on-chip (NoC) interconnects have emerged as viable architectures for Single-Instruction/Multiple-Data (SIMD) vector applications and parallel workloads, and have been implemented in 65nm CMOS with Dynamic Voltage-Frequency Scaling (DVFS) [1,2]. Chips with SingleVoltage/Single-Frequency (SVSF) for all cores running homogeneous threads [1] as well as Multiple-Voltage/Multiple-Frequency (MVMF), running heterogeneous applications and using independent V/F control for each core [2], have been reported. Combination of DVFS with dynamic core-count scaling (or DVFCS) has been proposed to further improve performance & energy efficiency across varying workloads [3]. With technology scaling, both leakage power and core-tocore variations in frequency (Fmax) & leakage due to within-die dev
Saurabh Dighe1, Sriram Vangal1, Paolo Aseron1, Shasi Kumar2,