A Power-Efficient 32b ARM ISA Processor Using Timing-Error Detection and Correction for TransientError Tolerance and Adaptation to PVT Variation

📋 论文概要

该论文提出一种基于时序错误检测和纠正的32位ARM处理器，通过组合错误检测电路与微架构恢复机制，允许动态消除保护带，从而在低电压下高效运行并容忍瞬态误差。

💡 主要创新点

• 采用Razor触发器实现时序错误检测，无需传统保护带即可可靠工作。
• 微架构级错误恢复机制，支持流水线重放或类似操作以纠正错误。
• 通过动态电压和频率调节（DVFS）自适应消除保护带，提升能效。

🏷 关键词

📄 原文摘要

detection and correction of timing errors. A combination of error-detecting circuits and micro-architectural recovery mechanisms creates a system which is robust in the face of timing errors, and can be tuned to an efficient operating point by dynamically eliminating unused guardbands. Canary or tracking circuits [4-5] can compensate for certain manifestations of PVT variation. However they still require substantial margining to account for fast-moving or localized events, such as Ldi/dt, local IR drop, capacitive coupling, or PLL jitter. These events are often transient, and while the pathological case of all occurring simultaneously is extremely unlikely, it cannot be ruled out. A Razor system can survive both fast-moving and transient events, and adapt

👥 作者与机构

David Bull1, Shidhartha Das1, Karthik Shivshankar1, Ganesh Dasika2,

Krisztian Flautner1, David Blaauw2 1 ARM, Cambridge, United Kingdom University of Michigan, Ann Arbor, MI 2 Razor [1-3] is a hybrid technique for dynamic