Bang-Bang Digital PLLs at 11 and 20GHz with sub200fs Integrated Jitter for High-Speed Serial Communication Applications

📋 论文概要

该论文提出了两款基于bang-bang鉴相器架构的数字锁相环（DPLL），工作频率分别为11GHz和20GHz，实现了低于200fs的集成抖动，适用于高速串行通信。解决了传统电荷泵PLL在面积、可测试性和灵活性方面的局限，同时避免了高性能DPLL中所需的时间数字转换器（TDC）及其量化限制。

💡 主要创新点

• 采用bang-bang鉴相器代替TDC，简化了数字PLL架构并避免了量化噪声。
• 在11GHz和20GHz频率下实现了sub-200fs的极低集成抖动，满足高速串行通信的严格相位噪声要求。
• 可能通过优化环路带宽和数字算法实现了宽调谐范围与低抖动的兼顾。

🏷 关键词

📄 原文摘要

Z. Toprak Deniz, D. Friedman IBM T.J. Watson Research Center, Yorktown Heights, NY Wireline communication applications typically require a low-phase-noise wide-tuning-range PLL. While these requirements can be met using traditional charge-pump PLL architectures, a high-performance digital PLL (DPLL)based solution offers potential advantages in area, testability, and flexibility. Nearly all high-performance DPLL architectures reported in the literature to date (see, e.g., [1-3]) incorporate a time-to-digital converter (TDC) that acts as the loop’s PFD. Subject to its quantization limits, a high-resolution TDC generates output signals proportional to the phase error at its input, effectively linearizing the PFD response. It should be noted, however, that reported high-performance TDC-based DPLLs have generally been fractional-N, i.e., not integer-N, synthesizers. In a fractional-N loop, the phase difference

👥 作者与机构

A. Rylyakov, J. Tierno, H. Ainspan, J.-O. Plouchart, J. Bulzacchelli,