A 14mW 5Gb/s CMOS TIA with Gain-Reuse Regulated Cascode Compensation for Parallel Optical Interconnects

📋 论文概要

该论文提出了一种用于并行光互连的CMOS跨阻放大器（TIA），采用增益复用型共源共栅补偿技术，在14mW功耗下实现5Gb/s的数据速率。解决了低功耗、高速TIA在并行光接收机中的设计难题。

💡 主要创新点

• 提出增益复用型共源共栅补偿（Gain-Reuse Regulated Cascode Compensation）技术，在维持低功耗的同时有效提升带宽。
• 采用差分结构设计，增强电源噪声抑制能力，适用于单芯片集成的大规模并行阵列。

🏷 关键词

📄 原文摘要

Hugh J. Barnaby, Bert Vermeire, Sayfe Kiaei Arizona State University, Tempe, AZ Short-distance parallel optical links are poised to replace copper interconnects in high throughput links between computing nodes. In the receiver front-end of such systems, one- and two-dimensional monolithically integrated arrays of power- and area-efficient TIAs are required [1]. Differential signaling is preferred for superior supply rejection while power consumption per amplifier unit should be minimized to avoid heat dissipation issues and to maintain the energy efficiency (J/bit) advantage over copper interconnect. On the other hand, lower gain is acceptable due to the intended short-haul application. Multi-Gb/s CMOS TIAs suffer from a fundamental BW limit at the input. As illustrated in Fig. 5.6.1, the TIA input sees significant extrinsic capacitive loading (CIN), not only from the photodiode (CPD) which is dominant, but also from

👥 作者与机构

Sushmit Goswami, Jason Silver, Tino Copani, Wenjian Chen,