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本文提出了一种用于10.3125Gb/s突发模式时钟数据恢复(CDR)电路的抖动降低和脉冲宽度失真(PWD)补偿电路。该CDR架构采用门控VCO(GVCO)实现低功耗，能在14位内完成同步，并有效抑制高频抖动和容忍较大的PWD。
burst-mode CDR circuit must be able to retime and reshape the input data. In this paper, a burst-mode CDR circuit is presented that achieves output-datajitter reduction of 3dB at jitter frequency of 1GHz, synchronization to the input data within 14 bits of the burst input, and tolerance to pulse-width distortion (PWD) of +0.22/−0.32UI at 10.3125Gb/s operation. These characteristics are provided by a CDR architecture with jitter-reduction and PWD-compensation circuits. A burst-mode CDR circuit using gated VCOs (GVCOs) has a simple architecture, so the power consumption is low and the circuitry is compact. In addition, the architecture provides instantaneous phase locking, which reduces the overhead time and increases transmission efficiency. One
Jun Terada1, Yusuke Ohtomo1, Kazuyoshi Nishimura1, Hiroaki Katsurai1,
Shunji Kimura2, Naoto Yoshimoto2 1 NTT, Atsugi, Japan, 2NTT, Chiba, Japan In burst transmission systems such as passive optical networks (PONs), a