A 7.1mW 10GHz All-Digital Frequency Synthesizer with Dynamically Reconfigurable Digital Loop Filter in 90nm CMOS

📋 论文概要

该论文提出了一种在90nm CMOS工艺下实现的10GHz全数字频率合成器，通过动态可重构数字环路滤波器替代传统无源环路滤波器，解决了电荷泵锁相环中的电容泄漏、电流失配和动态范围受限等问题。

💡 主要创新点

• 采用双模式鉴频鉴相器（PFD）和可编程积分器数字环路滤波器，实现动态可重构。
• 全数字架构避免了模拟电路的非理想效应，降低了功耗并提高了灵活性。

🏷 关键词

📄 原文摘要

ADPLL frequency synthesizers have recently drawnsignificant research attention as the technology paradigm shifts into the nanometer CMOS arena [1-5]. They circumvent several design issues that conventional charge-pump-based PLLs encounter, including capacitor leakage, current mismatch, and limited dynamic range. Furthermore, they benefit from replacing the bulky passive loop filter by a more cost-effective and flexible digital filter. The architecture of the presented ADPLL is illustrated in Fig. 5.1.1. It is composed of a dual-mode PFD, a PI digital loop filter composed of programmable integral (α) and proportional (β) paths, a locking process monitor (LPM), an LC-based DCO, a divide-by-4 prescaler, and two phase accumulators PAC1 and PAC2. The PAC1 accumulates quarter of the frequency multiplication factor (N/4) while PAC2 accumulates the prescaler output phase. The phase difference (ΦE) between fREF and fOUT/N is then resolved by a subtractor. The dualmode PFD is operated in the lin

👥 作者与机构

Song-Yu Yang, Wei-Zen Chen

National Chiao Tung University, Hsinchu, Taiwan