Subharmonically Injection-Locked PLLs for UltraLow-Noise Clock Generation

📋 论文概要

本文提出并验证了亚谐波注入锁定技术，能显著降低PLL相位噪声，成本极低。基于该技术实现了两个20GHz PLL，分别达到149fs_rms和85fs_rms的抖动，功耗仅38mW和105mW。

💡 主要创新点

• 完整分析了亚谐波注入锁定的相位噪声抑制机理，证明了锁定范围内相位噪声可被抑制至注入噪声水平加上20log10N。
• 采用亚谐波注入锁定技术实现了超低抖动和低功耗的20GHz PLL，性能领先。
• 无需额外复杂电路即可获得接近理想注入锁定的噪声性能，具有低成本优势。

🏷 关键词

📄 原文摘要

In this paper, complete analysis and validation of subharmonic injection locking that can substantially reduce the PLL phase noise at negligible cost is presented. Two 20GHz PLLs based on this technique demonstrate 149 and 85fsrms jitter while consuming 38 and 105mW, respectively. For an oscillator under fundamental injection locking, the phase noise within the lock range ωL will be suppressed to that of the injection signal [1, 2]. It is thus deducible that for a subharmonic locking with a frequency ratio N, the phase noise inside the lock range ωL would be constrained to Linj+20log10N, where Linj denotes the phase noise of the subrate injection signal CKinj. Since usually the lock range of an LC-tank VCO is not only small but sensitive to PVT

👥 作者与机构

Jri Lee1, Huaide Wang1, Wen-Tsao Chen2, Yung-Pin Lee2, 1

National Taiwan University, Taipei, Taiwan Industrial Technology Research Institute, Hsinchu, Taiwan 2 High-speed low-noise clocks are essential in numerous applications