A 5.4mW 0.0035mm2 0.48psrms-Jitter 0.8-to-5GHz Non-PLL/DLL All-Digital Phase Generator/Rotator in 45nm SOI CMOS

📋 论文概要

该论文提出了一种基于全数字架构的非PLL/DLL相位生成器/旋转器，采用45nm SOI CMOS工艺，在0.8-5GHz频率范围内实现了0.48psrms的低抖动和5.4mW的低功耗，面积仅为0.0035mm²。通过使用有源多相滤波器和相位插值技术，实现了160步的360度相位旋转，解决了传统PLL/DLL锁定时间长的问题。

💡 主要创新点

• 采用全数字架构，无需PLL或DLL，消除了锁定时间并简化了设计。
• 利用CMOS有源多相滤波器和相位插值器，在宽频率范围内实现精细的相位旋转步进（160步/360°）。
• 在极小的芯片面积（0.0035mm²）和低功耗（5.4mW）下实现了亚皮秒级抖动性能。

🏷 关键词

📄 原文摘要

Seongwon Kim1, Sergey V. Rylov1, Daniel J. Friedman1 1 IBM T.J. Watson, Yorktown Heights, NY IBM, Austin, TX 3 IBM, Poughkeepsie, NY and nine 4× legs, yielding a total of 40 realizable steps within a quadrant and 160 steps within a full 360°. The variable strength inverter output is sent to a poly-phase filter, realized as a CMOS active poly-phase filter (APF) as described in [5] in this design. A total of 5 stages of APF are cascaded in the test circuit to minimize I-Q phase error. Finally, the output of the last APF stage is connected to a phase interpolation stage to implement variable phase offset between data and edge sample timing [6]. This interpolation stage uses the same variable strength inverter as that used for phase rotation, but with a smaller number of legs in the phase offset stage. 2 A CDR circuit for serial link receivers usually requires a multi-phase generator and a number of phase rotators to produce data and edge clocks. The most

👥 作者与机构

Kyu-hyoun Kim1, Daniel M. Dreps2, Frank D. Ferraiolo3, Paul W. Coteus1,