A VDSL2 CPE AFE in 0.15µm CMOS with Integrated Line Driver

📋 论文概要

该论文实现了一个用于VDSL2 CPE的模拟前端（AFE），集成线路驱动器，采用0.15µm CMOS工艺。解决了VDSL2宽带信号（30MHz带宽）下高线性度要求（失真低于-65dBc）的问题，支持DMT调制以实现超过200Mb/s的比特率。

💡 主要创新点

• 将线路驱动器与AFE集成在同一芯片上，降低了系统成本和功耗。
• 针对VDSL2的6频带DMT信号，实现了满足-65dBc失真要求的模拟前端设计。

🏷 关键词

📄 原文摘要

VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200Mb/s. For standard 6-band VDSL2, 30MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete multi tone (DMT) modulation is used, distortion components for the signal chain have to be below −65dBc to fully exploit 15b-per-tone bit loading

👥 作者与机构

Giovanni Cesura1, Alessandro Bosi1, Francesco Rezzi1, Rinaldo Castello2,

Jenkin Chan3, SaiBun Wong3, Chi Fan Yung3 , Ovidiu Carnu4, Thomas Cho4 1 Marvell, Pavia, Italy, 2University of Pavia, Pavia, Italy, Marvell, Hong Kong, China, 4Marvell, Santa Clara, CA 3