A 56GHz 23mW Fractional-N PLL with 110fs Jitter

📋 论文概要

该论文提出一种56GHz分数-N锁相环（PLL），适用于224Gb/s PAM-4多通道发射器，在每通道内实现紧凑低功耗时钟生成。通过优化架构和电路设计，在23mW功耗下实现110fs均方根抖动，满足高速链路对低抖动和分数-N操作的需求。

💡 主要创新点

• 采用分数-N架构以适应不同晶振频率，同时避免多通道间56GHz时钟的远距离传输，降低系统复杂度。
• 通过低功耗设计技术和紧凑版图，在23mW功耗下实现110fs的超低抖动，满足PAM-4符号周期8.93ps的严格抖动要求。

🏷 关键词

📄 原文摘要

PAM-4 wireline transmitters operating at 224Gb/s can employ a 56GHz PLL for multiplexing. Such an environment poses several constraints on the design. First, the PLL rms jitter must be no more than a few percent of the symbol period, 8.93ps, dictating values around 100fsrms. Second, the PLL should preferably provide fractional-N operation so as to accommodate different crystal frequencies. Third, in a multi-lane system, it is desirable to avoid distributing a 56GHz clock over long interconnects, hence the need for a lower-power, compact PLL that can be used within each lane. Prior fractional-N designs in this frequency range have achieved rms jitters ranging from 200 to 500fs while consuming beween 31 and 46mW and occupying areas from 0.38 to 0.55mm2 [14]. This paper introduces a PLL with a jitter of 110fs that draws 23mW and occupies an area of 0.1mm2 in 28nm CMOS technology. Fractional-N PLLs typically face two severe issues, namely, noise folding due to charge

👥 作者与机构

Yu Zhao, Onur Memioglu, Behzad Razavi

University of California, Los Angeles, CA