A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET

📋 论文概要

本文提出了一种112Gb/s PAM-4长距离有线收发器，采用36路时间交织SAR-ADC和基于反相器的接收模拟前端，解决了数据中心和通信应用中高速长距离传输的挑战。

💡 主要创新点

• 采用36路时间交织SAR-ADC架构，实现了112Gb/s PAM-4信号的高精度模数转换。
• 基于反相器的接收模拟前端设计，降低了功耗并提高了线性度，支持长距离传输。

🏷 关键词

📄 原文摘要

Stanley Chen1, Yipeng Wang2, Hao-Wei Hung2, KeeHian Tan2, Winson Lin1, Arianne Roldan1, Declan Carey3, Ilias Chlis3, Ronan Casey3, Ade Bekele1, Ying Cao1, David Mahashin1, Hong Ahn1, Hongtao Zhang1, Yohan Frans1, Ken Chang1 Xilinx, San Jose, CA, 2Xilinx, Singapore, Singapore, 3Xilinx, Cork, Ireland 1 Interest in 112Gb/s wireline transceivers targeting data center and communication applications has rapidly increased. PAM-4 signaling remains the dominant choice of modulation scheme due to its superior spectral efficiency [1-2]. This paper reports a long-reach-capable 112Gb/s PAM-4 transceiver designed in 7nm FinFET. Figure 6.1.1 illustrates the top-level block diagram of the transceiver, comprised of a shared LC-PLL, a transceiver channel, and a control block. The control block sends 875MHz 128b-wide TX data and receives 778MHz 144b-wide RX data to and from transceiver channels and calculates the PRBS bit error rate (BER). The

👥 作者与机构

Jay Im1, Kevin Zheng1, Adam Chou1, Lei Zhou1, Jae Wook Kim1,