A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters

📋 论文概要

本文提出了一种用于超过400Gb/s相干光通信的线性驱动IC，采用堆叠电流复用架构在65nm CMOS工艺中实现48GHz带宽和225mW/ch功耗，解决了高符号率（>64GBaud）和高阶调制（>16-QAM）下对宽带驱动器的需求。

💡 主要创新点

• 采用堆叠电流复用架构，在65nm CMOS中同时实现了高带宽（48GHz）和低功耗（225mW/ch）。
• 针对相干光通信系统，设计了线性驱动电路以满足高阶调制格式的线性度要求。

🏷 关键词

📄 原文摘要

attention for constructing large-capacity optical core/metro networks and even data center interconnects. Data rates in the next generation of coherent optical transmission systems are expected to exceed 400Gb/s, for which transceivers that can handle symbol rates over 64GBaud and modulation orders over 16-QAM are necessary. Regarding the transmitter, the Optical Internetworking Forum (OIF) is discussing a 64GBaud-class high-bandwidth coherent driver modulator (HB-CDM), which is a broadband electro-optic (EO) front-end module containing optical modulator drivers and Mach-Zehnder modulators (MZMs) [1]. In addition to operating speed, power consumption is also important because it limits the form factor. It is important to reduce the power consumption of the optical modulator driver – one of the most power-hungry blocks in the transmitter – while maintaining a sufficient

👥 作者与机构

Teruo Jyo, Munehiko Nagatani, Josuke Ozaki, Mitsuteru Ishikawa, Hideyuki Nosaka

NTT, Kanagawa, Japan Digital coherent optical transmission technologies are attracting much