⚡ 本页包含 AI 生成的分析内容,仅供参考
该论文提出了一款基于DSP的112Gb/s PAM-4收发机,采用7nm FinFET工艺,功耗仅460mW,具备38dB的损耗补偿能力,旨在满足下一代数据中心51.2Tb/s交换机的需求。
Yu-Ming Ying1, Mohammed Abdullatif1, Miguel Gandara1, Chun-Cheng Liu2, Po-Shuan Weng2, Huan-Sheng Chen2, Mohammad Elbadry1, Qaiser Nehal1, Kun-Hung Tsai2, Kevin Tan2, Yi-Chieh Huang2, Chung-Hsien Tsai2, Yuyun Chang2, Yuan-Hao Tung2 MediaTek, Irvine, CA MediaTek, Hsinchu, Taiwan *Equally-Credited Authors (ECAs) 1 2 Explosive growth in mega-scale data centers drives switch chips to transition from 12.8Tb/s to 51.2Tb/s throughput. A 51.2Tb/s switch requires 512 lanes operating at 106Gb/s PAM-4. Such a massive integration of electrical SERDES is restrained by three factors: First, a large switch die size (>25"25mm2) substantially lowers yield and prohibitively increases cost. Second, a large-size package suffers more than 10dB insertion loss from combined TX and RX traces. Considering practical equalization capabilities of a long-reach system (>30dB), 10dB package loss significantly limits the available channel reach. Lastly, channel reflection and
Tamer Ali*1, Ehung Chen*1, Henry Park*1, Ramy Yousry*1,