A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver

📋 论文概要

该论文提出了一种基于SiGe BiCMOS工艺的4-to-1模拟时间交织器，实现了100GS/s的采样率，功耗为700mW。解决了CMOS DAC在采样率和带宽上的限制，通过主动组合多个DAC来提升性能。

💡 主要创新点

• 采用4-to-1模拟时间交织架构，有效提升采样率至100GS/s
• 基于SiGe BiCMOS工艺实现，兼顾高速与低功耗
• 主动组合方式替代被动分布式拓扑，优化带宽和效率

🏷 关键词

📄 原文摘要

DACs with an analog bandwidth (BW) of at least 50GHz to support advanced modulation schemes. CMOS-based DACs are preferred because they support monolithic integration of the DSP and DAC, but the achievable sampling rate and BW is limited [2]. To increase the sampling rate, multiple DACs can be passively or actively combined. A passive combiner using a distributed topology

👥 作者与机构

Hannes Ramon, Michiel Verplaetse, Michael Vanhoecke, Haolin Li,

Johan Bauwelinck, Peter Ossieur, Xin Yin, Guy Torfs imec-Ghent University, Ghent, Belgium Future 100Gbaud DSP-enabled optical coherent transceivers [1] will need 100GS/s