A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

📋 论文概要

该论文提出了一款采用10nm FinFET工艺的56Gb/s PAM-4有线收发器，通过基于MM-CDR的ADC时序偏移控制技术解决了高速ADC采样时钟偏差问题，并实现了7.7mW/Gb/s的低功耗设计。

💡 主要创新点

• 提出基于MM-CDR（多模时钟数据恢复）的ADC时序偏移控制技术，有效补偿多通道ADC间的采样时钟偏差。
• 采用低功耗DSP架构和优化电路设计，在56Gb/s PAM-4传输下实现7.7mW/Gb/s的能效比。

🏷 关键词

📄 原文摘要

Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin Samsung Electronics, Hwaseong, Korea Needs for I/O bandwidth have rapidly increased with the explosive growth of internet traffic and data technologies. To accommodate the required high bandwidth, a DSP-based PAM-4 transceiver became the most robust solution with increased usage of channel capacity [1-4]. However, to be integrated with many transceivers in a chip, low-power designs are becoming critical factors for DSP-based transceivers. This paper presents an MM-CDR-based ADC timing skew control, which greatly reduces ADC complexity and power, and a low-power DSP using an approximate multiplier. Besides this, gm boosting of the TX driver and low-power TX DAC help reduce total power consumption.

👥 作者与机构

Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee,