A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1dB FoM Using a Proportionally Divided Charge Pump

📋 论文概要

本文提出了一种具有480倍乘法因子的13.2-17.3GHz子采样锁相环（PLL），在仅6.6mW功耗下实现了-248.1dB的FoM。该设计通过优化子采样结构和比例路径，有效解决了大乘法因子下高频频率合成器的相位噪声与功耗挑战。

💡 主要创新点

• 提出一种480倍高乘法因子的子采样PLL架构，在降低功耗的同时保持了低相位噪声性能。
• 设计优化的比例路径，使得在13.2-17.3GHz范围内实现-248.1dB的优异FoM，显著优于传统级联PLL方案。

🏷 关键词

📄 原文摘要

Beyond-10GHz frequency synthesizers are ubiquitous building blocks for today’s evergrowing wireless and wireline communication systems. To meet the stringent requirements on data-rate and modulation schemes, the phase noise of the frequency synthesizers must be minimized. On the other hand, since low-noise and low-cost crystal oscillators operate in the MHz range, a >10GHz frequency synthesizer demands a very large multiplication factor M (typically 400-1000), which poses new challenges. Although cascading PLLs helps reduce M per stage, it causes a significant power overhead and unwanted coupling between the two VCOs. Therefore, direct high M-factor frequency synthesis with low phase noise and low power consumption becomes a compelling approach. Subsampling PLLs (SSPLLs) are superior for generating low phase noise signals, as the divider noise is eliminated, and the phase noise of the detector/charge pump (PD/CP) is

👥 作者与机构

Luya Zhang, Ali Niknejad

University of California, Berkeley, CA