⚡ 本页包含 AI 生成的分析内容，仅供参考
本文针对高性能系统中多芯片封装间的单端链路提出了一种参考噪声补偿方案，解决了参考电压噪声引起的信号完整性下降问题，从而实现了可靠的高速数据传输。
Brian Zimmer1, Thomas H. Greer2, John W. Poulton2, Sanquan Song1, Walker J. Turner2, John M. Wilson2, C. Thomas Gray2 NVIDIA, Santa Clara, CA NVIDIA, Durham, NC 1 2 A recent trend in high-performance systems is distribution of computing across many chips and packages to sustain performance scaling while achieving high yield and alleviating power delivery. High-end data center systems and new applications like deep neural network (DNN) accelerators with scalable architecture [1] may extend the system from large chip-scale computing not just to package-scale multi-chip modules (MCM), but also to PCB-scale computing systems. An essential requirement for these distributed systems is a highly scalable low-power and high-bandwidth interconnect system, that can cover a wide range of integration and channel distances. Ideally, the same low-power links designed for ultra-short reach interconnects in MCM should be used in more
Xi Chen1, Nikola Nedovic1, Stephen G. Tell2, Sudhir S. Kudva1,