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ISSCC 2022Session 17 · ADVANCED WIRELINE LINKS AND TECHNIQUESWireline I/O28nm CMOS

A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS

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📋 论文概要

该论文提出了一种基于模拟域处理的DP-QPSK相干光接收机,在28nm CMOS工艺下实现了200Gb/s的数据速率和4.6pJ/b的能效,解决了传统ADC-DSP方案在短距光互连中功耗过高的问题。

💡 主要创新点

核心指标
4.6pJ/b @ 200Gb/s
工艺节点
28nm CMOS
重要性
发表年份
ISSCC 2022

🏷 关键词

相干光接收机模拟信号处理DP-QPSK

📄 原文摘要

cloud computing, have significantly driven the requirement for high transmission data rates. Polarization diversity coherent detection is an indispensable technique for realizing high-capacity transmission owing to its excellent spectral efficiency. ADC-DSP-based coherent receivers [1-2] have been widely deployed in long-haul optical systems, but the high power consumption prohibits their application in power-sensitive short-reach links like 5G mobile backhaul networks, arousing eagerness for power-efficient analog solutions. An analog coherent receiver is proposed in [3], where a single-stage equalizer is used to compensate for chromatic dispersion (CD) and rotation of state of polarization (SOP), resulting in complex interconnection, large parasitic capacitance, and consequently limited data rate. In this paper,

👥 作者与机构

Kai Sheng*, Haowei Niu*, Boyang Zhang*, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen

Peking University, Beijing, China *Equally-Credited Authors (ECAs) Emerging bandwidth-hungry applications such as

分类:Wireline I/O · 年份:ISSCC 2022