⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款采用3nm FinFET CMOS工艺的224Gb/s PAM-4收发器，实现了3pJ/b的能效和40dB的插入损耗补偿，旨在满足数据中心800G/1.6T交换机及AI加速器对更高I/O带宽的需求。
Mohammad-Mahdi Mohsenpour1, Marc-Andre LaCroix1, Babak Zamanlooy3, Tom Eeckelaert1, Dmitry Petrov1, Mostafa Haroun1, Carson Dick2, Alif Zaman1, Haitao Mei1, Shahab Moazzeni1, Tahseen Shakir1, Carlos Carvalho1, Howard Huang1, Pratibha Kumari1, Ralph Mason1, Fahmida Brishty2, Ifrah Jaffri2 Synopsys, Ottawa, Canada Synopsys, Mississauga, Canada 3 Synopsys, Markham, Canada 1 2 With datacenters introducing 800G/1.6T switches and emerging artificial intelligence accelerator ASICs demanding higher aggregate I/O bandwidth, 224Gb/s PAM-4 transceivers are expected to supersede today’s dominant 112Gb/s SERDES. Such transceivers must double analog I/O bandwidth to 56GHz while maintaining or exceeding the previous generation’s energy efficiency. This requires substantial improvements in the data and clock paths. With the baud rate doubled, channel losses exceeding 35dB must be addressed by higher order digital equalizers and optional maximum likelihood
Dirk Pfaff1, Muhammad Nummer1, Noman Hai2, Peter Xia2, Kai Ge Yang2,